The present invention relates to a non-volatile semiconductor memory device. More particularly, the invention relates to a Least Significant Bit (LSB) read method for a non-volatile memory device and a memory system including same.
The use of data storage devices such as volatile memories and nonvolatile memories has greatly expanded in applications related to mobile devices such as MP3 players, PMPs, mobile phones, notebook computers, PDAs, and the like. These mobile devices increasingly demand large data storage capabilities in order to provide high-end functionality, such as video recording, editing and playback. In order to satisfy these demands, multi-bit memory devices have been developed which are capable of storing N-bit data per memory cell, wherein N is 3 or more.
Exemplary multi-bit memory devices are disclosed, for example, in U.S. Pat. Nos. 6,122,188; 6,075,734; and 5,923,589, the collective subject matter of which is hereby incorporated by reference.
In a case where 1-bit data is stored in each memory cell of a memory cell array, each properly programmed memory cell will have a threshold voltage within one of two (2) defined threshold voltage distributions. That is, a memory cell will have one of two possible data states corresponding respectively to data values of ‘1’ or ‘0’. In contrast, in a case where 2-bit data is stored in each memory cell, each properly programmed memory cell will have a threshold voltage within one of four (4) defined threshold voltage distributions. That is, a memory cell will have one of four possible states respectively corresponding to data values of ‘11’, ‘10’, ‘01’ and ‘00’.
When the threshold voltage of a memory cell is increased to a threshold voltage above the so-called erased state (or, the ON state), the memory cell is said to be “programmed’. Figure (FIG.) 1 is a diagram describing a programming method for a NAND flash memory device comprising two-bit memory cells. Referring to FIG. 1, the two-bit memory cell is programmed using a LSB program operation and a Most Significant Bit (MSB) program operation. That is, the NAND flash memory device programs 2-bit data using a MSB program operation that follows a LSB program operation.
Accordingly and as illustrated in FIG. 1, the two-bit memory cell may reside at any given time in one of three possible programming states; (a) an erased state, (b) a LSB-programmed state, and (c) a MSB-programmed state. One exemplary procedure for programming the two-bit memory cell will now be described.
A case is assumed wherein a data value of ‘10’ is programmed to a 2-bit memory cell currently residing in an erased state. Thus, the ‘0’ value is the LSB of data and the ‘1’ value is the MSB of data. Following execution of the LSB program operation, the memory cell will have a threshold voltage that corresponds to either the ‘11’ data or the ‘10’ data. Then, the MSB program operation is carried out, and the threshold voltage of the memory cell will migrate (a) from a threshold voltage corresponding to ‘11’ data to either ‘11’ data or ‘01’ data, or (b) from a threshold voltage corresponding to ‘10’ data to either ‘00’ data or ‘10’ data.
Within this overall programming procedure, the threshold voltage of a flag cell may be used to determine whether a selected page of memory cells has been properly MSB programmed. That is, based upon a threshold voltage position of the flag cell, a selected page may be judged to be either LSB programmed or MSB programmed.
A NAND flash memory device may perform an LSB program operation or an MSB program operation in response to a read command and an address that are externally provided (e.g., from a memory controller). In general, a received page address may be identified as a LSB page address and a MSB page address. Accordingly, a NAND flash memory device may determine whether the LSB program operation or the MSB program operation should be performed based on a read command and the received address. An exemplary LSB read operation and MSB read operation will be described in some additional detail with reference to FIGS. 2 and 3.
FIG. 2 is a flowchart summarizing an LSB read operation operative within a NAND flash memory device comprising two-bit memory cells. The LSB read operation begins when the NAND flash memory device determines that a read operation indicated by an input read command is an LSB read operation. This determination may be made according to the received input address. If the read operation indicated by the input read command is an LSB read operation, the NAND flash memory device may read data from the memory cells of a selected page in relation to a second read voltage R2 (S111). The selected page is assumed to include a flag cell used to indicate whether the selected page is LSB programmed or MSB programmed.
Thus, a determination is made as to whether the threshold voltage of the flag cell is higher than the second read voltage R2 (S112). A flag cell threshold voltage less than the second read voltage R2 indicates that the memory cell is LSB programmed. A flag cell threshold voltage greater than the second read voltage R2 indicates that the memory cell is MSB programmed.
If the flag cell threshold voltage is less than the second read voltage R2 (S112=no), the NAND flash memory device reads data from the memory cells of the selected page using a first read voltage R1 (S113). That is, if the selected page is LSB programmed, the NAND flash memory device may again read data from memory cells of the selected page using the first read voltage R1.
A determination is now made as to whether the threshold voltage of the memory cells in the selected page are greater than the first read voltage R1 (S114). In other words, the NAND flash memory device determines the value of LSB data for each memory cell in the selected page based upon whether its threshold voltage is greater than the first read voltage R1. If the threshold voltage of respective memory cells in the selected page is greater than the first read voltage R1, then a LSB data value of ‘0” is indicated (S117). If the threshold voltage of respective memory cells in the selected page is less than the first read voltage R1, then a LSB data value of ‘1” is indicated (S116).
However, if the flag cell threshold voltage is greater than the second read voltage R2 (S112=yes), a determination is made as to whether the threshold voltage of each memory cell in the selected page is greater than the second read voltage R2 (S115). That is, if the selected page is determined to be MSB programmed, the LSB data of each memory cell may be determined based on whether the threshold voltage of each memory cell in the selected page is greater than the second read voltage R2.
As understood from the above description, if the threshold voltage of respective memory cells in the selected page is less than the second read voltage R2 (S115=no), an LSB data value of ‘1’ is indicated (S116). If the threshold voltage of respective memory cells in the selected page is greater than the second read voltage R2 (S115=yes), an LSB data value of ‘0’ is indicated (S117).
FIG. 3 is a flowchart summarizing an MSB read operation for a NAND flash memory device comprising two-bit memory cells. The MSB read operation begins when the NAND flash memory device determines that a read operation indicated by an input read command is an MSB read operation. This determination may be made according to the received input address. If the read operation indicated by the input read command is an MSB read operation, the NAND flash memory device may read data from the memory cells of a selected page in relation to the first read voltage R1 (S211). The selected page is again assumed to include a flag cell used to indicate whether the selected page is LSB programmed or MSB programmed.
The NAND flash memory device determines whether the flag cell threshold voltage is less than the first read voltage R1 (S212). If the selected page is determined to be MSB programmed, the flag cell threshold voltage will be greater than the first read voltage R1.
If the flag cell threshold voltage is greater than the first read voltage R1 (S212=no), the NAND flash memory device nest determines whether the threshold voltage of each memory cell in the selected page is less than the first read voltage R1 (S213).
If the threshold voltage of each memory cell in the selected page is greater than the first read voltage R1 (S213=no), the data stored in the memory cells of the selected page may be again read using a third read voltage R3 (S214).
After the stored data is read from the memory cells of the selected page, a determination is made as to whether the threshold voltage of each memory cell in the selected page is greater than the third read voltage R3 (S215). If the threshold voltage of each memory cell in the selected page is less than the third read voltage R3 (S216=no), the MSB data for each memory cell is determined to be data ‘0’. On the other hand, if the flag cell threshold voltage is greater than the first read voltage R1 (S212=yes), or if the threshold voltage of each memory cell is less than the first read voltage R1 (S213=no), or if the threshold voltage of each memory cell is greater than the third read voltage R3 (S215=no), then the MSB data is determined to be data ‘1’ (S217).
As illustrated in FIG. 1, the conventional flag cell may be maintained in the erase state (i.e., data ‘11’) during the LSB program operation, but may then be programmed into data ‘10’ during the MSB program operation. However, the flag cell may suffer from voltage variations due to a number of reasons including, for example, read voltage stress, write voltage stress, coupling, power-off effects, etc. In such cases, the flag cell may not properly retain a desired data state during one or both of the LSB and MSB program operations. This may cause a data error when data is read from a selected page programmed in relation to errant flag cell voltage.
FIG. 4 further illustrates a case wherein a flag cell voltage is disturbed during a LSB program operation. Referring to FIG. 4, the threshold voltage of the flag cell is intended to indicate data ‘10’. However, due to some external effect, the flag cell threshold voltage becomes greater than the second read voltage R2. As a result, during a LSB read operation a memory cell having a threshold voltage between the first and second read voltages R1 and R2 may be erroneously read from the memory cells in the selected page. That is, assuming that normal LSB data for a memory cell is ‘0’, the LSB data for the memory cell may be read as ‘1’ due to a disturbed flag cell threshold voltage.
Additionally, if a power is turned OFF during the MSB program operation of a NAND flash memory device, there may be damaged data in the MSB page, as well as data in the LSB page sharing the same word line as the MSB page. This result usually occurs when a power is turned OFF while the flag cell is being programmed to a data ‘10’ state from a data ‘11’ state.
FIG. 5 further illustrates a case wherein a flag cell is disturbed when power is turned OFF during a MSB program operation. Referring to FIG. 5, it is assumed that the flag cell has a threshold voltage between the second read voltage R2 and the third read voltage R3 corresponding to a data state of ‘X0’. In this case, data in a memory cell may be erroneously read during a subsequently applied LSB read operation. That is, normal LSB data of a memory cell is ‘0’. But, during the subsequent LSB read operation, the LSB data of the memory cell may be read as ‘1’ due to the disturbed flag cell.
FIG. 6 further illustrates a case wherein a flag cell is disturbed when a power is turned OFF during a MSB program operation. Referring to FIG. 6, it is assumed that a threshold voltage of a flag cell resides within a threshold voltage distribution corresponding to a data ‘10’ state. In this case, data in a memory cell may be erroneously read out during a subsequently applied LSB read operation. That is, normal LSB data of the memory cell is ‘0’, but the LSB data of the memory cell may be read as ‘1’ due to the disturbed flag cell.
As described above in multiple cases, a conventional NAND flash memory device may erroneously read LSB data due to a disturbed flag cell. Further, it is often impossible to recover erroneously read LSB data via conventional LSB read methods.